The present invention relates to flash memory devices, and more particularly to a method and system for providing a contact in a flash memory device in which alignment, for example to a field oxide, is not critical.
Semiconductor memories are finding increasing use in many devices. For example, FIG. 1 depicts a portion of a dynamic random access memory (DRAM) 10 during fabrication. The DRAM 10 is formed using a semiconductor substrate 11 and includes polysilicon lines 14. Between polysilicon lines 14 is a junction 12. The polysilicon lines 14 are also separated by spacers 15. The polysilicon lines 14 are covered by an etch stop layer 16 and an insulator 17. In order to make contact to the junction 12, a contact hole 18 has been etched in the insulator 17. The etch stop layer 16 has a different etch selectivity than the insulator 17. Consequently, an etch of the insulator does not greatly etch the etch stop layer 16. Once the contact hole 18 has been etched, the portion of the etch stop layer 16 exposed by the contact hole 18 can be removed, the contact hole filled with a conductor and processing of the DRAM can be completed. Consequently, the DRAM 10 can be used.
Although the DRAM 10 can be used as a memory device, one of ordinary skill in the art will readily realize that the DRAM 10 is a volatile memory. The DRAM 10 cannot retain its information when no power is provided to. the DRAM 10. Consequently, the DRAM 10 cannot be used for many applications.
Flash memory devices are a popular form of nonvolatile storage. Flash memory devices can, therefore, retain information when no power is supplied to the device. Flash memory devices include memory cells that include a gate stack, a source and a drain. Unlike the conventional DRAM 10, each gate stack typically includes a floating gate. Each gate stack also includes a control gate separated from the floating gate by an insulating layer. The insulating layer is typically-a composite ONO layer including two oxide layers separated by a nitride layer. Some memory cells may be separated by field oxide regions. Contact is made to the source and drain regions.
FIG. 2A depicts a conventional method 20 for providing a conventional flash memory device. Field oxide regions, gate stacks, source and drain regions, and spacers are provided, via step 22. An insulating layer is provided on the gate stacks and field oxide regions, via step 24. Contact holes are then etched in the insulating layer by very carefully aligning a mask to expose the regions to be etched and etching the exposed regions of the insulating layer, via step 26. The contact holes are typically provided over the source or drain regions. Contact holes may also be provided for other structures. However, the contact holes to make contact to the source or drain region are typically the deepest. The contact holes are then filled using a conductive material, via step 30. Processing of the conventional flash memory device can then be continued, via step 32.
FIG. 2B depicts a portion of a conventional flash memory device 50 formed using the method 20. The conventional flash memory device includes a gate stack 60 formed on a semiconductor substrate 51. Adjacent to the gate stack 60 is a field oxide region 52. The field oxide region is separated from the gate stack by a source/drain region 54. Because the source and drain in a flash memory cell are typically similar from the standpoint of contact formation, such regions will be referred to as source/drain regions. Another source/drain region 56 is located on an opposing side of the gate stack 60. The gate stack 60 includes a floating gate 64 separated from the substrate 51 by an oxide layer 62, an insulating layer 66 and a control gate 68. The floating gate 64 and control gate 68 are typically formed of polysilicon. The insulating layer 66 is typically a composite, ONO layer composed of two layers of oxide separated by a nitride layer. Spacers 63 and 65 may also be provided. The field oxide region 52, gate stack 60 and source/drain regions 54 and 56 have been covered by an insulating layer 70. A contact hole 72 has been etched- into the insulating layer, via step 26 of the method 20. The contact hole 72 has been filled with conductive material 74. Consequently, contact can be made to the source/drain region 54.
Although the conventional flash memory device 50 functions, one of ordinary skill in the art will readily realize that the contact can be misaligned during the photolithography process. In particular, if the alignment of the mask used to etch the contact holes in step 26 of the method 20 is not very carefully controlled, a portion of the field oxide region may be exposed during the etch of the contact hole 72. The field oxide region 52 is also typically composed of a material that is the same as or, in terms of etch selectivity, very similar to the insulating layer 76. Furthermore, endpoint detection is difficult because contact holes occupy a very small percentage of the surface of the flash memory devices. Consequently, conventional optical emission techniques may not be capable of detecting when the field oxide 52 or source/drain regions 54 are exposed. As a result, the contact holes 72 are typically over-etched to ensure that the electrical contact can be made to the source/drain regions 54. The field oxide region 72 may thus be easily punched through during the contact hole etch, exposing a portion of the underlying substrate 51, when contact holes 72 are misaligned. Making electrical contact to both the source/drain region 54 and the underlying silicon substrate 51 is undesirable. Moreover, it may be very difficult, if not impossible, to properly align the contact hole 72. Thus, a mechanism for accounting for misalignments must be used in forming the conventional flash memory device 50.
In order to account for misalignments during etching of contact holes, another conventional method has been developed. FIG. 3A depicts another conventional method 20xe2x80x2 for providing a conventional flash memory device. The conventional method 20xe2x80x2 is very similar to the conventional method 20. Consequently, similar steps will be labeled similarly. Field oxide regions, gate stacks and source and drain regions are provided, via step 22xe2x80x2. An insulating layer is provided on the gate stacks and field oxide regions, via step 24xe2x80x2. Contact holes are then etched in the insulating layer, via step 26xe2x80x2. The contact holes are typically provided over the source or drain regions. Because of misaliginments which may occur, an additional implant is typically provided, via step 28. The implant is of the same type as the source and drain implants. Thus, the implant provided in step 28 is typically a p+implant. The contact holes are then filled using a conductive material, via step 30xe2x80x2. Processing of the conventional flash memory device can then be continued, via step 32xe2x80x2.
FIG. 3B depicts a conventional flash memory device 50xe2x80x2 in which the contact is misaligned and in which the method 20xe2x80x2 has been used for fabrication. The conventional flash memory device 50xe2x80x2 has essentially the same components as the conventional flash memory device 50 depicted in FIG. 3A. Corresponding structures are, therefore, labeled similarly. For example, the gate stack 60xe2x80x2 of the conventional flash memory 50xe2x80x2 corresponds to the gate stack 60 of the conventional flash memory 50 shown in FIG. 3A. Referring back to FIG. 3B, the contact hole 72xe2x80x2 is slightly misaligned. As a result, a portion of the contact hole 72xe2x80x2 is above the field oxide region 52xe2x80x2. The field oxide region 52xe2x80x2 is, therefore, etched when the contact hole 72xe2x80x2 is etched into the insulating layer 70xe2x80x2. As depicted, the etch which formed the contact hole 72 has punched through the edge of the field oxide region 72xe2x80x2, exposing a portion of the underlying semiconductor substrate 51xe2x80x2. In order. to ensure that the conductor 74xe2x80x2 filling the contact hole 72xe2x80x2 is not exposed to varying doping concentrations, an additional doped region 76 is provided in the conventional semiconductor device 50xe2x80x2. Using step 28 of the conventional method 20xe2x80x2, the additional doped region 76 is provided by performing an additional implant after the contact holes have been etched.
Although the conventional flash memory cell 50xe2x80x2 functions, one of ordinary skill in the art will readily realize that an additional dopant is provided in the contact holes. Providing this additional dopant complicates processing. However, without the additional doped region, the alignment of the mask used during the contact hole etch must be very carefully performed. Consequently, use of either the method 20 or the method 20xe2x80x2 is undesirable.
Accordingly, what is needed is a system and method for providing contacts for a flash memory device which is simpler and for which alignment is not as critical. The present invention addresses such a need.
The present invention provides a method and system for providing a plurality of contacts in a flash memory device. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system comprise providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also comprise providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further comprise etching the insulating layer to provide the contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also comprise filling the plurality of contact holes with a conductor.
According to the system and method disclosed herein, the present invention provides flash memory device contacts in a manner which is simpler and does not require as precise alignment.